The present invention relates to acquisition of high-frequency analog signals.
Analog memories have been employed in the acquisition of high-frequency analog signals, particularly to facilitate reading the analog signals out of memory at a slower rate than they were stored so that the acquired analog signals may be processed by circuits having relaxed bandwidth requirements. Serial analog memories in the form of sample-hold elements disposed along and activated by the outputs of a high-speed shift register have been effective in the acquisition of high-frequency analog signals. However, to adequately store a complete waveform, such a serial analog memory requires a shift register which is fairly long, for example, 100 elements or more in length.
Prior serial analog memories have been implemented using large-scale integration (LSI) technology to produce metal-oxide-semiconductor (MOS) chips with the entire memory, including the shift register, sample-hold elements, and analog bus, on the chip. Operation of a shift register on a complementary-metal-oxide-semiconductor (CMOS) chip is limited to about 25 megahertz, which limits the sampling rate. Further, for a 100-element shift register, an external clock must drive 100 shift register flip-flops at several times the frequency of the analog signal. A further problem is that in the readout mode of operation, the MOS capacitors associated with the sample-hold elements must drive a relatively large capacitance associated with the analog bus, resulting in a substantial attenuation of the analog signal voltage.